MODELSIM ALTERA QUARTUS II HOW TO

I could look into how to do that in SystemVerilog, however I'm now just wondering how this is normally done.Р”В®dit: NVM not sure why but trying the packages/pkg_timer.sv method now works. This is similar to what happens in C / C++ if you include a file twice (from within the same file), to get around it you use: #ifndef _FILE_NAME_H This then fails in Quartus with 'identifier TimerPackage' is already declared in the previous scope. Р”Р‡inally I tried changing my package file to timer.pkg and using a `include from the top of every file that needs that package definition. This of course fails as when it tries to compile a file that uses my package. However when I go to tools->run simulate tool->RTL simulation, Modelsim opens and tries to run: Test_run_msim_rtl_verilog.do which seems to be an auto generated script that compiles all my (non-testbench) files EXCEPT my package file, and then calls my msim_compile.do script. Vlog -sv -work work +incdir+PATH/packages

I have Quartus set up to use a custom compile script for modelsim, which is called msim_compile.do and looks like. I then tried moving the package definition into another file packages/pkg_timer.sv, added that to my list of files at the top and all is great. package TimerPackage Р”Р„t first I had this at the top of my Timer.sv file, but then it only works if my files are compiled in the correct order, which with just one package is fine, I can just make sure Timer.sv is first in the list, but that sounds like bad practice. To allow passing this in from other modules I have the enum defined in a package. I want to use an enum here for clarity, so I can have ACTION_NONE and ACTION_TOGGLE. I'm working a module, one parameter is a single bit input.

Modelsim altera quartus ii